`timescale 1ns / 1ps
`include "defines.vh"
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/06/10 14:00:18
// Design Name: 
// Module Name: ROM
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


// 从ROM提取指令
module ROM(

    input [0:0] rst,
    input [0:0] clk,

    input [`Instruction_Addr_Bus] Instruction_addr_Input,
    output [`Instruction_Bus] Instruction_Output,

    input [0:0] Clear_flag_Input
    );

    wire [`Instruction_Bus]Instruction_Output_wire;


    always @(posedge clk) begin
        $display($time,"    ROM:  In => in_addr:%d,Clear_flag:%d, Out => out_ins: %d",Instruction_addr_Input,Clear_flag_Input,Instruction_Output);
    end

    // 复位或暂停或地址超出范围时输出默认值
    assign Instruction_Output = (rst == `Rst_Enabled  | Clear_flag_Input == `Clear_Flag_Enabled | Instruction_addr_Input > 32'h4000) ? `ROM_Rst : Instruction_Output_wire;





    TO_ROM TO_ROM(
        //ROM大小 16384 * 32 = 2^14 * 32   右移2位，相当于除4
        .a (Instruction_addr_Input[13:0] >> 2),
        .spo (Instruction_Output_wire)
    );





endmodule
